1. Field of the Invention
This invention relates to a semiconductor memory device of the type having a one-transistor/one-cell structure as formed on a silicon-on-insulator (SOI) substrate.
2. Description of Related Art
Recently, for the purpose of alternative use or replacement of conventional dynamic random access memory (DRAM) devices, a semiconductor memory device that has a more simplified cell structure for enabling achievement of dynamic storability has been proposed. This type of memory is disclosed, for example, in Takashi Ohsawa et al., “Memory Design Using One-Transistor Gain Cell on SOI”, ISSCC Digest of Technical Papers, 2002, pp. 152-153. A memory cell is structured from a single transistor which has an electrically floating body (channel body) as formed on a silicon on insulator (SOI) substrate. This memory cell offers two-value data storing capabilities while regarding the state that an excess number of majority carriers are accumulated or stored in the body as a first data state (for example, logic “1” data) and letting the state that the excessive majority carriers are drawn out from the body be as a second data state (e.g. logic “0” data).
The one-transistor memory cell of the type stated above will be referred to hereinafter as a floating-body cell (FBC). A semiconductor memory using FBCs will be called the “FBC memory”. The FBC memory makes use of no capacitors unlike currently available standard DRAM chips so that this one-transistor/no-capacitor or “capacitor-less” cell memory is simpler in memory cell array structure and smaller in unit cell area than ever before. Thus FBC memory is readily scalable in cell structure and advantageously offers much enhanced on-chip integration capabilities.
For writing logic “1” data in the FBC memory, impact ionization near the drain of a memory cell is utilized. More specifically, while giving appropriate bias conditions for permitting flow of a significant channel current in the memory cell, cause majority carriers that are produced by impact ionization be stored in the floating body. Writing logic “0” data is performed by setting a PN junction between the drain and the body in a forward bias state to thereby release the body's majority carriers toward the drain side.
A difference in the carrier storage states of such floating body appears as a difference in threshold voltage of a transistor. Thus it is possible to determine or sense whether the resultant read data is a logic “0” or “1” by detecting whether an appreciable cell current is present or absent—alternatively, whether the cell current is large or small in magnitude—while applying a prespecified read voltage to the gate of a presently selected memory cell. Excess majority carriers of the body would be drawn out through the PN junction between the source and drain when letting the body remain unprocessed for an increased length of time period. Thus a need is felt to perform refresh operations at constant time intervals as in ordinary DRAMs.
For improving the characteristics of the FBC memory, it has also been proposed to employ in addition to the main gate of a memory cell an auxiliary gate which is capacitively coupled to the floating body. This approach has been disclosed, for example, in Published Japanese Patent Application Nos. 2002-246571 and 2003-31693.
Techniques for fabricating laterally structured or “lateral-access” bipolar transistors on an SOI substrate are known, one of which is disclosed for example in IEEE Transactions on Electronic Devices, Vol. 49, No. 3, March 2002, pp. 414-421.
In semiconductor memories using bulk semiconductor, techniques are known for using bipolar transistors in sense amplifier circuitry to perform high-speed reading, some of which are found in U.S. Pat. No. 4,658,159 (assigned to Toshiba), U.S. Pat. No. 5,287,314 (to Motorola); U.S. Pat. No. 5,265,060 (Hitachi); and U.S. Pat. No. 4,839,862 (NEC). A technique for using bipolar transistors for bit-line selector circuitry is also known and is taught by U.S. Pat. No. 5,371,703 (Toshiba).
In FBC memories, the same bias relationship is used during data reading and during logic “1” data writing. Thus at the time of data readout, it should be required that the drain voltage of a presently selected memory cell is potentially lower than that at the time of logic “1” write in order to ensure that no write failures take place—in other words, no impact ionization occurs at the selected memory cell. Due to this, it is not easy to permit flow of a larg cell current during data reading and therefore to obtain increased sensitivity of sense amplifier circuitry. If it is unable to flow a large cell current, then an increased length of time must be taken for charging/discharging a bit line as connected to the drain of a memory cell. This in turn makes it impossible to perform high-speed reading operations required.
In order to achieve high-speed reading of FBC memories, it is also required to speed up the potential rise-up and fall-down of a word line used to drive the gate of a memory cell. In other words, large current drivability is required also to a row decoder which drives the word line.